The vast majority of electronic devices employ integrated circuits which contain either or both NPN or PNP bipolar transistors. However, many integrated circuit arrangements are difficult to fabricate, using multiple exacting process steps that are costly in terms of processing material usage and time. Furthermore, often these processes are not optimized for fabrication of either the NPN or PNP transistors.
As the fabrication processes are not optimized, the electrical properties of the NPN bipolar transistor and of the PNP bipolar transistor are similarly not optimized. Thus, by way of example, during the patterning of a polycrystalline silicon layer arranged on an insulating layer in the region of the NPN transistor, it is difficult to effect a high degree of overetching to obtain steep sidewalls, which may be useful for the reproducibility of the transistor properties. More specifically, when etching a 200 nm thick polycrystalline layer, a high degree of overetching such as 100% overetching means a doubling of the etching duration used for etching the 200 nm.
However, the polycrystalline silicon layer is also used as a base connection region of the PNP transistor arranged alongside the emitter. During overetching of the polycrystalline silicon layer, the base connection region of the PNP transistor may be partly removed. This is problematic as the polycrystalline silicon layer is used simultaneously for the construction of the PNP and NPN transistors and is intended to be maintained in the PNP transistor.
FIG. 1 shows the fabrication of an integrated circuit arrangement 8 in accordance with the prior art. The integrated circuit arrangement 8 contains a p-doped substrate (not illustrated) made of silicon. An n-type epitaxial layer 10 is situated on the substrate. The epitaxial layer has been n-doped at its surface in the region of the PNP transistor. The dopant concentration in the doping region 12 is, for example, 1018 dopant atoms per cubic centimeter, so that the doping region 12 is suitable for forming a base region of the PNP transistor. Situated below the doping region 12 is a doping region 14, in which a p-type doping of, for example, 1017 doping atoms per cubic centimeter has been produced.
In the region of the NPN transistor, a doping region 16 is situated at the surface of the n-type epitaxial layer 10. The doping region 16 is n-doped and has, in this production stage, for example the basic doping of the n-type epitaxy of 1016 doping atoms per cubic centimeter. The doping region 16 is doped even more highly later as the collector region of the NPN transistor.
An insulating layer 18 is situated on the n-type epitaxial layer 10. The insulating layer 18, for example, has a thickness of 100 nm and comprises silicon dioxide. The insulating layer 18 has a large-area cutout in the region of the PNP transistor, and so it is not illustrated in FIG. 1. By contrast, the insulating layer 18 is present and still unpatterned in the region of the NPN transistor, in particular above the doping region 16.
After the application of the insulating layer 18, a heavily p-doped polycrystalline silicon layer 20 is deposited over the whole area. By way of example, the number of doping atoms in the polysilicon layer 20 is 1020 doping atoms per cubic centimeter. In the region of the PNP transistor, the polysilicon layer 20 contacts the doping region 12 as the insulating layer 18 is absent in this region. In the region of the NPN transistor, by contrast, the polysilicon layer 20 contacts the insulating layer 18.
An insulating covering layer 22 is applied above the entire polysilicon layer 20. Afterward, photoresist 24 is applied to the covering layer 22, exposed and developed, with the result that the regions of the photoresist 24 which are illustrated in FIG. 1 have remained, that is to say above an emitter connection region of the PNP transistor and above a base connection region of the NPN transistor.
Etching is subsequently carried out to pattern the covering layer 22 and to pattern the underlying polysilicon layer 20, for example with the aid of reactive ion etching, see arrows 26 and 28. The reactive ion etching is carried out during the etching of the polysilicon layer 20 selectively with respect to the insulating layer 18. In order to completely eliminate oblique sidewalls 30 of the polysilicon layer 20 in the region of the NPN transistor, a high degree of overetching is used. The doping region 12 is severed in the region of the PNP transistor on account of the high degree of overetching during the etching of the polysilicon layer 20. Therefore, only a weak degree of overetching is effected, the doping region 12 being incipiently etched and its original thickness D1 thus being reduced by a thickness D2. What is more, the selectivity in the region of the PNP transistor during the etching of the polysilicon layer 20 is considerably lower, on account of the silicon lying below the polysilicon layer 20, than the selectivity in the region of the NPN transistor, where the insulating layer 18 made of silicon dioxide lies below the polysilicon layer 20.
As a result the base connection region being thinned, the base connection resistance increases, which reduces the maximum oscillation frequency and increases the minimum noise figure and delay times of the integrated circuit. In addition, the reproducibility of the transistor quantities is reduced.
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.